1. Field of the Invention
The present invention relates to semiconductor devices and methods for their construction. More particularly, the present invention relates to capacitor design and cell isolation methods used to reduce the surface area occupied by a DRAM cell. More specifically, the present invention merges capacitor design and cell isolation methods by using existing isolation trench sidewalls to form a DRAM capacitor thus increase DRAM cell density by at least about two fold over currently fabricated DRAM cells.
2. Background Art
Various DRAM capacitor designs have been employed to reduce the surface area occupied by a single DRAM cell. Early DRAM designs employed flat horizontal capacitor plates. Later designs, intended to conserve chip surface area, employed trenches or fin structures to form narrow dimension capacitors with some vertical contribution to the capacitor plate surface area.
In addition to the shape and size of the capacitor plates, the type of cell isolation contributes to the overall DRAM cell size. Traditionally, field oxide produced by the LOCal Oxidation of Silicon process (LOCOS) was used as cell isolation. Unfortunately, a field oxide must cover a fairly wide area in order to effectively isolate adjacent cells. Further, it is difficult to control the growth of field oxide. Therefore, field oxide often occupies a significant amount of the chip surface area.
More recently, trench isolation has been employed. This involves etching a narrow isolation trench around the active areas (cells) on the chip. The isolation trenches are then filled with oxide or other dielectric to effectively isolate adjacent active areas from one another. While trench isolation requires more process steps than field oxide isolation, trench isolation can be made much narrower than field oxide isolation. Therefore, DRAMs employing trench isolation can be packed more densely than DRAMs employing field oxide (LOCOS) isolation.
In the continuing quest for higher density DRAMs, improved structures employing trench isolations are still needed.
The present invention addresses this need by providing a DRAM cell where existing isolation trench sidewalls are used to form a DRAM capacitor. Integration of capacitor formation with DRAM cell isolation increases DRAM cell density by at least about two fold over currently fabricated DRAM cells.
In one aspect, the instant invention provides a DRAM cell comprised of a pass (or access) transistor electrically coupled with the capacitor and an isolation trench on a semiconductor substrate. The isolation trench electrically isolates the DRAM cell from one or more adjacent DRAM cells. The capacitor is comprised of a first capacitor plate, a dielectric layer and a second capacitor plate. The first capacitor plate is defined by the semiconductor substrate at the wall of the isolation trench. The second capacitor plate is defined by a conductive layer inside the isolation trench. The first and second capacitor plates are separated by the dielectric layer.
The pass transistor is a MOS device that may have a drain electrically connected to the second capacitor plate and electrically isolated from the first capacitor plate. In one embodiment, the isolation trench has a depth of at least about 0.3 micrometers. In another embodiment, the isolation trench has a width of at most about 0.5 micrometers. Preferably, the isolation trench is at least partially filled with a dielectric material.
In a specific embodiment, the first capacitor plate has a substantially greater dopant concentration than immediately adjacent semiconductor substrate. The second capacitor plate occupies a portion of the isolation trench proximate to the pass transistor. The conductive layer that comprises the second capacitor plate is preferably doped polysilicon. It may be between about 200 angstroms and about 2000 angstroms thick.
The dielectric layer may be made from any suitable material that can be formed in the necessary size and shape. Suitable dielectric materials include at least one of SiO2, Si3Nx, silicon oxynitride, ONO (silicon oxide/silicon nitride/silicon oxide layered material), tantalum pentaoxide (Ta2O5), barium strontium titanate ((Ba, Sr) Ti O3 (xe2x80x9cBSTxe2x80x9d)), and piezoelectric lead zirconate titanate (xe2x80x9cPZTxe2x80x9d). Preferably, the dielectric layer comprises a material with a high dielectric constant (e.g., at least about 10) such as BST, PZT, or Ta2O5. In one specific embodiment, the dielectric layer is Ta2O5 and is between about 20 and about 200 angstroms thick depending on the capacitor plate area.
In another aspect, the invention provides a method for forming a capacitor in an isolation trench of an integrated circuit. The process is characterized by forming an isolation trench in a semiconductor substrate and then forming a capacitor in the isolation trench. Later, the trench is filled with isolation dielectric.
In one embodiment, the isolation trench includes both a capacitor dielectric and an isolation trench dielectric which occupy different areas of the isolation trench. This does not preclude embodiments where the isolation dielectric and the capacitor dielectric are made from the same material; although one will generally want an isolation dielectric with a relatively low dielectric constant and a capacitor dielectric with a relatively high dielectric. In one embodiment, the isolation trench is etched to a depth of at least about 0.5 micrometers. In another embodiment, the isolation trench is formed to a width of at most about 0.25 micrometers.
The capacitor is formed by a process that may be characterized as having the following sequence: (a) forming the first capacitor plate in the semiconductor substrate immediately adjacent the sidewalls of the isolation trench; (b) forming a capacitor dielectric layer on part of the sidewalls of the isolation trench; and (c) forming a second capacitor plate on a part of the capacitor dielectric.
The first capacitor plate may be formed by a process where a dopant source material is provided on a portion of the isolation trench sidewalls. This material furnishes a source of dopant atoms which are driven into the adjacent semiconductor substrate. The dopant source material may be conformally deposited on the trench sidewalls and then selectively removed from the top portion of the isolation trench. The location of the remaining source material defines the location of the first capacitor plate. The dopant source material may be removed from the top of the vertical sidewalls of the isolation trench by a process that may be characterized as having the following sequence: (a) depositing photoresist in the isolation trench; (b) exposing the photoresist to a specific depth in the isolation trench; (c) developing the photoresist (to remove the exposed upper part of the photoresist); and (d) removing the dopant source material from the top portion of the vertical sidewalls of the isolation trench.
The process may subsequently strip or otherwise remove the photoresist from the isolation trench. Then an oxide may be deposited to cap the dopant source material and prevent diffusion at the top portion of the trench. Ultimately, the device is annealed to drive dopant from the source material into the adjacent substrate, thereby forming the first capacitor plate. Thereafter, the source material is removed from the treanch.
In one embodiment, the dopant source material is a boron doped glass. In a specific embodiment, the boron doped glass is deposited to a thickness of between about 100 angstroms and about 2,000 angstroms. In another specific embodiment, the boron doped glass has a dopant concentration of between about 1xc3x971018 and about 1xc3x971022 atoms/centimeter3.
The capacitor dielectric may be provided by a process similar to that employed to form and shape the dopant source material. Specifically, the capacitor dielectric may be conformally deposited and then removed from the top of the vertical sidewalls of the isolation trench. The capacitor dielectric may be removed from the top of the vertical sidewalls of the isolation trench by a process that may be characterized as having the following sequence: (a) depositing photoresist over the isolation trench; (b) exposing the photoresist to a specific depth in the isolation trench; (c) developing the photoresist; (d) removing the capacitor dielectric from the top portion of the vertical sidewalls of the isolation trench. Thereafter, the process may strip or otherwise remove the photoresist from the isolation trench.
The second capacitor plate may be provided by a process comprising (a) conformally depositing a layer of conductor such as polysilicon or titanium nitride (or platinum in the case of BST dielectric) in a portion of the isolation trench followed by (b) an anisotropic etch that preferentially removes polysilicon from the bottom surface of the isolation trench while retaining polysilicon at the vertical sidewall of the isolation trench to form the second capacitor plate.
These and other features and advantages of the present invention will be further described in the following detailed description of the invention with reference to the associated drawings.